Embodiments of the present invention relate to matched capacitor arrays, and more particularly to reducing capacitance variations within a matched capacitor array.
Various integrated circuits, such as analog-to-digital converters, digital-to-analog converters, switch capacitor filters, and the like, utilize matched capacitor arrays. As integrated circuit technology progresses, the matching of such capacitor arrays requires ever increasing precision. The precision to which the capacitors can be matched is influenced by the physical uniformity of the capacitor structures and the electrical coupling between adjacent capacitors.
For parallel plate capacitor structures, which are typically utilized in matched capacitor arrays, the capacitance is proportional to the area of the overlapping plates and inversely proportional to the separation thereof. Furthermore, as minimum feature sizes decrease, it becomes increasingly more difficult to maintain the uniformity of structures. Hence, it also becomes more difficult to reduce capacitance variations. For example, alignment errors increase as the number of masks required for forming the structure increases. Furthermore, the planarity of the wafer surface degrades as layers are formed thereupon. The non-planar surface introduces non-uniformity in the thickness of the layers formed thereupon. The non-planar surface also introduces non-uniformity in the line edges of the patterned photo mask, and hence the line edges of the etched structures.
Referring to FIGS. 1A-1B, top and side section views of a capacitor array 100, in accordance with the conventional art, is shown. The capacitor array 100 comprises a plurality of top plates 105 and a plurality of bottom plates 110. The top 105 and bottom 110 plates are separated by a dielectric material 115. Each individual top plate 105 is aligned with a respective bottom plate 110 to form a capacitor (e.g., C1-C16). Typically, the top plates 105 are electrically connected in common. Individual electrical connections are provided to each bottom plate 110.
The interior edges of the individual capacitors 120, 125 along the periphery of the array 100 each have an adjacent capacitor; while the exterior edges of the individual capacitors 130, 135 do not have an adjacent capacitor. The deposition, lithography and etching processes utilized in forming the various structures are influenced by non-uniformity of the surface that they act upon. Thus, the presence or absence of adjacent structure may result in a wider or narrower dielectric layer along an edge, which results in variations in the separation between the plates. The presence or absence of adjacent structure may also result in a wider or narrower line edge in the top and/or bottom plates, which results in variations in the area of the plates. The primary capacitance of each capacitor is influenced by such variations in the adjacent structure.
The physical structure of the various capacitors in the array 100 are influenced differently. For example, the capacitors at the corners (e.g., C1) only have adjacent structures on two sides. The capacitors along the periphery (e.g., C5), but not the corners, have adjacent structures on three sides. While the capacitors in the interior (e.g., C6) of the array have adjacent structures on all four sides. Therefore, various capacitors will have different primary capacitance values.
In addition, as the separation between adjacent capacitors is reduced, parasitic capacitance, caused by the cross-coupling of oppositely disposed plates of adjacent capacitors, increases. The presence or absence of adjacent capacitors influences the parasitic capacitances of the various capacitors. For example, the capacitors at the corners (e.g., C1, C4, C13, C16) of the array 100 have two adjacent capacitors. Therefore, the corner capacitors (e.g., C1, C4, C13, C16) have two parasitic capacitances contributing to their total capacitance. The capacitors along the periphery of the array 100 (e.g., C2, C3, C5, C8, C9, C12, C14, C15) have adjacent structures on three sides. Therefore, the capacitors along the periphery (e.g., C2, C3, C5, C8, C9, C12, C14, C15) have three parasitic capacitances contributing to their total capacitance. The capacitors in the interior of the array 100 (e.g., C6, C7, C10, C11) have adjacent structures on all four sides. Therefore, the interior capacitors (e.g., C6, C7, C10, C11) have four parasitic capacitances contributing to their total capacitance. Thus, various capacitors will have different parasitic capacitance values.
For the exemplary capacitor array 100 shown in FIG. 1, the total capacitance for each capacitor is represented by the equations in Table 1. For example, the total capacitance of capacitor C1 is equal to the sum of the primary capacitance C1-1 of capacitor C1, the cross-coupled capacitance C1-2 between capacitors C1 and C2, and the cross-coupled capacitance C1-5 between capacitors C1 and C5.
The combined cross-coupling between a particular capacitor and multiple adjacent capacitors is referred to hereinafter as interdigitating capacitance.
Accordingly, conventional capacitor arrays suffer from variations in the physical (e.g., geometric) properties of the individual capacitors. Thus, precise capacitance matching in conventional capacitor arrays is problematic due to the physical variations. Conventional capacitor arrays also suffer from variations in the interdigitating capacitance of the individual capacitors. Thus, precise capacitance matching in conventional capacitor arrays is problematic due to parasitic capacitance variations.
A capacitor array, having substantially matched capacitances, is disclosed. In one embodiment, the capacitor array comprises a plurality of core capacitors arranged in a plurality of rows and a plurality of columns. A plurality of guard capacitors are arranged such that there is a guard capacitor at the beginning and end of each of the rows and columns of core capacitors. A plurality of fringe capacitors are arranged between the guard capacitors and the core capacitors. The top plates of the core capacitors and the top plates of the fringe capacitors are coupled to a first node of a circuit. The top and bottom plates of the guard capacitors and the bottom plates of the fringe capacitors are coupled to ground. Each of the bottom plates of the core capacitors are independently coupled to a respective independent node of the circuit. The various capacitors of the array and the means for coupling them are uniformly distributed such that each core capacitor is uniformly influenced by its adjacent structure. As a result, variations in the primary capacitance of each core capacitor are substantially reduced. The total capacitance of each core capacitor also has substantially equal parasitic capacitance components.